Interference suppression
Intelligent suppression for degraded RF and IF signals in dynamic interference conditions.
PELIAN SDRPSR100
Intelligent Software Defined Radio
Robust reception in interference-challenged environments.
A compact intelligent Software Defined Radio designed to improve effective SINR and reception robustness in dynamic, congested and interference-challenged RF environments. Intelligent embedded signal processing works with a high-performance RF transceiver platform to improve link reliability without increasing transmit power.
For receiver-side RF integration, laboratories, satellite links and field validation.
PSR100 / PELIAN SDRSOURCE PHOTOGRAPH
400 MHz–6 GHzFrequency coverage
Up to 50 MHzInstantaneous bandwidth
FPGAReal-time processing
8–12 WTypical power consumption
System benefits / 01
Intelligent processing at the point of reception.
The Pelian signal path is designed to condition challenging RF environments before the waveform reaches existing downstream equipment.
Improved effective SINR
Improves effective SINR and receiver robustness under interference.
Cleaner waveform delivery
Conditions RF and IF waveforms before delivery to existing receivers or modems.
Real-time processing
FPGA-based streaming signal processing supports continuous receiver-side operation.
Deterministic low latency
A deterministic architecture supports inline operation where predictable processing matters.
Integrator-ready subsystem
Designed for RF and IF chains, laboratory trials, field validation and system integration.
Mission-relevant scenarios
Supports GNSS, telemetry, tracking and command, and satellite data-link contexts.
No added transmit power
Improves reception performance without requiring an increase in transmit power.
Application contexts / 02
Engineered for demanding receive environments.
Application contexts describe intended areas of integration and evaluation; they do not imply deployment certification.
GNSS reception
Telemetry, tracking and command
Satellite data links
RF and IF laboratory validation
Receiver-side signal conditioning
Field trials and system integration
Architecture / 03
A clear, deterministic signal path.
A simplified functional view of the product architecture and its control interface.
RF Front-End
Configurable 400 MHz–6 GHz RF platform
Intelligent Processing Core
FPGA-based real-time signal processing
Baseband Output
Conditioned waveform delivery
Embedded CPU
1 Gigabit Ethernet
Technical specifications / 04
PSR100 at a glance.
Preliminary integration data reproduced from the supplied Pelian SDR product brief.
Preliminary specifications are subject to change without notice.
Technical enquiry